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cyil2sm1300aa lupa 1300-2: high speed cmos image sensor cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-24599 rev. *c revised september 18, 2009 features 1280 x 1024 active pixels 14 m x 14 m square pixels 1? optical format monochrome or color digital output 500 fps frame rate on-chip 10-bit adcs 12 lvds serial outputs random programmable roi readout pipelined and triggered snapshot shutter on-chip column fpn correction serial to parallel interface (spi) limited supplies: no minal 2.5v and 3.3v 0c to 70c operational temperature range 168-pin pga package power dissipation: 1350 mw applications high speed machine vision motion analysis intelligent traffic system medical imaging industrial imaging description the lupa 1300-2 is an integrated sxga high speed, high sensi?tivity cmos image sensor. this sensor targets high speed machine vision and industrial monitoring applications. the lupa 1300-2 sensor runs at 500 fps and has triggered and pipelined shutter modes. it packs 24 parallel 10-bit a/d converters with an aggregate conversion ra te of 740 msps. on-chip digital column fpn correction enables the sensor to output ready to use image data for most applications. to enable simple and reliable system integration, the 12 channels, 1 sync channel, 8 gbps, and lvds serial link protocol supports skew correction and serial link integrity monitoring. the peak responsivity of the 14 m x 14 m 6t pixel is 7350 v.m2/w.s. dynamic range is measured at 57 db. in full frame video mode, the sensor consumes 1350 mw from the 2.5v power supply. the sensors integrate a/d conversion, on-chip timing for a wide range of operating modes, and has an lvds interface for easy system integration. by removing the visually disturbing column patterned noise, this sensor enables building a camera without any offline correction or the need for memory. in addition, the on-chip column fpn correction is more reliable than an offline correction, because it compensates for supply and tem perature variations. the sensor requires one master clock for operations up to 500 fps. the lupa 1300-2 is housed in a 168 pin pga package and is available in a monochrome version and bayer (rgb) patterned color filter array. the monochrome version is available without glass. contact your local cypress office. figure 1. lupa 1300-2 die photo note 1. contact your local sales office for the windowless option. ordering information marketing part number mono/color package cyil2sm1300aa-gzdc mono with glass 168 pin pga cyil2sm1300aa-gwces mono without glass [1] CYIL2SC1300AA-GZDC color with glass cyil2sm1300-eval mono demo kit demo kit [+] feedback
cyil2sm1300aa document number: 001-24599 rev. *c page 2 of 41 overview this data sheet describes the interface of the lupa1300-2 image sensor. the sxga resolution cmos active pixel sensor features synchronous shutter and a maximal frame rate of 500 fps in full resolution. the readout speed is boosted by sub sampling and the windowed region of interest (roi) readout. fpn correction cannot be used in conjunction with sub-sampling and windowed region of interest readout. high dynamic range scenes can be captured using the double and multiple slope functionality. user programmable row and column start and stop positions enables windowing. sub sampling reduces resolution while maintaining the constant field of view and an increased frame rate. the lupa1300-2 sensor has 12 lvds high speed outputs that transfer image data over longer distances. this simplifies the surrounding system. the lvds interface can receive high speed and wide bandwidth data signals and maintain low noise and distortion. a special training m ode enables the receiving system to synchronize the coming data stream when switching to master, slave, or trigger ed mode. the image sensor also integrates a programmable offs et and gain amplifier for each channel. a 10-bit adc converts the analog data to a 10-bit digital word stream. the sensor uses a 3-wire serial-parallel interface (spi). it requires only one master clock for operation up to 500 fps. the sensor is available in a monochrome version or bayer (rgb) patterned color filter array. it is placed in a 168-pin ceramic pga package. specifications table 1. general specifications parameter specifications active pixels 1280 (h) x 1024 (v) pixel size 14 m x 14 m pixel type 6t pixel architecture pixel rate 630 mbps per channel (12 serial lvds outputs) shutter type pipelined and triggered global shutter frame rate 500 fps at 1.3 mpixel (boosted by subsampling and windowing) master clock 315 mhz for 500 fps windowing (roi) randomly programmable roi read out up to four multiple windows read out windowed, flipped, mirrored, and subsampled read out possible adc resolution 10-bit, on-chip sensitivity 10.16 v/lux.s at 550 nm extended dynamic range multiple slope (up to 90 db optical dynamic range) table 2. electro optical specifications parameter value conversion gain 34v/e - full well charge 30000e - responsivity 7350 v.m 2 /w.s at 680 nm fill factor 40% parasitic light sensitivity < 1/10000 dark noise 37e - qe x ff 35% at 680 nm fpn 2% rms of the output swing prnu <1% rms of the output signal dark signal 170 mv/s at 30 c power dissipation 1350 mw [+] feedback
cyil2sm1300aa document number: 001-24599 rev. *c page 3 of 41 photovoltaic response curve figure 2. photo voltaic response of lupa 1300-2 spectral response curve figure 3. spectral response of lupa 1300-2 [+] feedback
cyil2sm1300aa document number: 001-24599 rev. *c page 4 of 41 figure 4. spectral response of lupa 1300-2 color sensor 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 400 500 600 700 800 900 1000 red green ? near ? red green ? near ? blue blue [+] feedback
cyil2sm1300aa document number: 001-24599 rev. *c page 5 of 41 electrical specifications exceeding maximum ratings may shorten the useful li fe of the device. user guidelines are not tested. table 3. absolute ratings [2] symbol parameter min max unit s v dig core digital supply voltage -0.5 5.5 v v in analog supply voltage -0.5 5.5 v i io dc supply current ma esd: hbm human body model 2000 v esd: cdm charged device model 500 v t j temperature range 0 70 c table 4. power supply ratings [3, 4, 5] boldface limits apply for t a =t min to t max , all other limits t a =+25c. clock = 315 mhz symbol power supply parameter condition min typ max units v ana , gnd ana analog supply operating voltage -5% 2.5 +5% v dynamic current clock enabled, lux=0 7 20 ma peak current clock enabled, lux=0 16 ma standby current shutdown mode, lux=0 1 ma v dig , gnd dig digital supply operating voltage -5% 2.5 +5% v dynamic current clock enabled, lux=0 80 120 ma peak current clock enabled, lux=0 130 standby current shutdown mode, lux=0 52 ma v pix, gnd pix pixel supply operating voltage -5% 2.5 +5% v dynamic current clock enabled, lux=0 6 50 ma peak current during fot clock enabled, lux=0, transient duration=9 s 1.4 a peak current during rot clock enabled, lux=0, transient duration=2.5 s 35 ma standby current shutdown mode, lux=0 1 ma v lvds , gnd lvds lvds supply operating voltage -5% 2.5 +5% v dynamic current clock enabled, lux=0 220 275 ma peak current clock enabled, lux=0 280 ma standby current shutdown mode, lux=0 100 ma v adc , gnd adc adc supply operating voltage -5% 2.5 +5% v dynamic current clock enabled, lux=0 210 275 ma peak current clock enabled, lux=0 260 ma standby current shutdown mode, lux=0 3 ma notes 2. absolute ratings are those values beyond which damage to the device may occur. 3. all parameters are characterized for dc condi tions after thermal equilibrium is established. 4. peak currents were measured without the load capacitor from the ldo (low dropout regulator). the 100 nf capacitor bank was co nnected to the pin in question. 5. this device contains circuitry to protec t the inputs against damage due to high static voltages or electric fields. however, it is recommended that normal precautions be taken to avoid application of any voltages higher than the maximum rated voltages to this high impedance circuit. [+] feedback
cyil2sm1300aa document number: 001-24599 rev. *c page 6 of 41 every module in the image sensor has its own power supply and ground. the grounds can be combined externally, but not all power supply inputs may be combined. some power supplies must be isolated to reduce electrical crosstalk and improve shielding, dynamic range, and output swing. internal to the image sensor, the ground lines of each module are kept separate to improve shielding and electrical crosstalk between them. the lupa 1300-2 contains circuitry to protect the inputs against damage due to high static voltages or electric fields. however, take normal precautions to avoid voltages higher than the maximum rated voltages in this high impedance circuit. unused inputs must always be tied to an appropriate logic level, for example, v dd or gnd. all cap_xxx pins must be connected to ground through a 100 nf capacitor. the recommended combinations of supplies are: analog group of +2.5v supply: v sample , v res_ds , v mem_l , v adc , v pix , v ana , v buf digital group of +2.5v supply: v dig , v lvds v buf , gnd buf buffer supply operating voltage -5% 2.5 +5% v dynamic current clock enabled, lux=0 30 50 ma peak current clock enabled, lux=0 85 ma standby current shutdown mode, lux=0 0.1 ma v sample , gnd sample sampling circuitry supply operating voltage -5% 2.5 +5% v dynamic current clock enabled, lux=0 2 ma peak current clock enabled, lux=0 42 ma standby current shutdown mode, lux=0 1 ma v res reset supply operating voltage -5% 3.5 +5% v dynamic current clock enabled, lux=0 2 15 ma peak current clock enabled, lux=0 65 ma standby current shutdown mode, lux=0 2 ma v res_ab antiblooming supply operating voltage -10% 0.7 +10% v dynamic current clock enabled, lux=0 1 ma peak current following edge reset clock enabled, lux=0 50 ma standby current shutdown mode, lux=0 1 ma v res_ds reset dual slope supply operating voltage -5% 2.5 +5% v dynamic current clock enabled, lux=0 0.4 3 ma peak current clock enabled, lux=0 36 ma v res_ts reset triple slope supply operating voltage -5% 1.8 +5% v dynamic current clock enabled, lux=0 0.3 2 ma peak current clock enabled, lux=0 14 ma v mem_l memory element low level supply operating voltage -5% 2.5 +5% v dynamic current clock enabled, lux=0 0.2 1 ma peak current during fot clock enabled, lux=0 62 ma peak current during fot clock enabled, bright 30 ma v mem_h memory element high level supply operating voltage -5% 3.3 +5% v dynamic current clock enabled, lux=0 1 ma peak current during fot clock enabled, lux=0 45 ma v prech pre_charge driver supply operating voltage -10% 0.7 +10% v dynamic current clock enabled, lux=0 0.3 3 ma peak current during fot clock enabled, lux=0 32 ma peak current during fot clock enabled, lux=bright 25 ma table 4. power supply ratings [3, 4, 5] (continued) boldface limits apply for t a =t min to t max , all other limits t a =+25c. clock = 315 mhz symbol power supply parameter condition min typ max units [+] feedback
cyil2sm1300aa document number: 001-24599 rev. *c page 7 of 41 sensor architecture the floor plan of the architecture is shown in figure 5 . the sensor consists of a pixel array, analog front end, data block, and lvds transmitters and receivers. separate modules for the spi, clock div ision, and sequencer are also in tegrated. the image sensor o f 1280 x 1024 pixels is read out in progressive scan. this architecture enables programmable addressing in the x-direc tion in steps of 24 pixels, and in the y-direction in steps of one pixel. the starting point of the address can be uplo aded by the serial parallel interface (spi). the afe prepares the signal for the digital data block when th e data is multiplexed and prepared for the lvds interface. figure 5. floor plan of the sensor table 5. power dissipation [3] these specifications apply for v dd = 2.5v, clock = 315 mhz, 500 fps symbol parameter condition typ units p down power down no clock running 400 mw power average power dissipation lux = 0 1350 mw table 6. ac elect rical characteristics [3] the following specifications apply for vdd = 2.5v, clock = 315 mhz, 500 fps. symbol parameter condition typ max units f clk input clock frequency fps = 500 315 mhz dc clk clock duty cycle at maximum clock 50 % fps frame rate maximum clock speed 500 fps image core 1280 x 1024 24 analog channels 31.5 msps analog front end 24x 10-bit digital channels 31.5 msps data block local register 12x 10-bit digital channels 63 msps lvds tx and rx 12x lvds outputs at 630 msps clock divider clk out clk in sequencer & logic spi 31.5 mhz 315 mhz 63 mhz clk x & clk y [+] feedback
cyil2sm1300aa document number: 001-24599 rev. *c page 8 of 41 the 6t pixel to obtain the global shutter feature combined with a high sensitivity and good parasitic li ght sensitivity (pls), implement the pixel architecture shown in figure 6 . this pixel architecture is designed in a 14 m x 14 m pixel pitch. the pixel is designed to meet the specifications listed in table 1 and table 2 on page 2. this architecture also enables pipelined or triggered mode, as shown in figure 6 . figure 6. 6t pixel architecture frame rate and windowing frame rate the frame rate depends on the input clock, the frame overhead time (fot), and the row overhead time (rot). the frame period is calculated by: frame period = fot+nr. lines * (r ot + nr. pixels * clock period) example readout of the full resolution at nominal speed (756 mhz pixel rate = 1.32 ns) frame period = 5 s + (1025 * (206 ns+1.32 ns*1296) = 1.97 ms => 507 fps the real speed of the lupa1300-2 is reduced to 500 fps, because overhead pixels are read out for black level calibration and other on board features. windowing windowing is easily achieved by spi. the starting point of the x and y address and the window size can be uploaded. the minimum step size in the x-direction is 24 pixels (choose only multiples of 24 as start or stop addresses). the minimum step size in the y-direction is one line (every line can be addressed) in normal mode, and two lines in sub sampling mode. the section sequencer on page 10 discusses the use of registers to achieve the desired roi. analog to digital converter the sensor has 24 10-bit pipelined adcs on board. the adcs nominally operate at 31.5 msamples/s. programmable gain amplifiers the pgas amplify the signal before sending it to the adcs. the amplification inside the pga is controlled by one spi setting: afemode [5:3]. six gain steps can be selected by the afemode<5:3> register. ta b l e 1 0 lists the six gain settings. the unity gain selection of the pga is done by the default afemode<5:3> setting. table 7. frame rate parameters parameter comment clarification fot frame overhead time programmable: default 315 mhz granularity clock cycles (5 s at 630 mhz) rot row overhead time programmable: default 13 granularity clock cycles (206 ns at 630 mhz) nr. lines number of lines read out each frame nr. pixels number of pixels read out each line clock period 1/63 mhz = 15.9 ns every channel works at 63 mhz ? 12 channels result in 756 mhz data rate vpix vmem reset sample select table 8. typical frame rates for 630 mhz clock image resolution (x*y) frame rate (fps) frame read out time (s) 1296x1025 507 1970 640 x 512 1842 550 256 x 256 6933 146 table 9. adc parameters parameter specification data rate 31.5 msamples/s quantization 10 bit dnl typ. < 1 dn inl typ. < 1 dn table 10. gain settings afemode<5:3> gain 000 1 001 1.5 010 2 011 2.25 100 3 101 4 [+] feedback
cyil2sm1300aa document number: 001-24599 rev. *c page 9 of 41 operation and signaling digital signals depending on the operation mode (master or slave), the pixel arra y of the image sensor requires different digital control signa ls. the function of each signal is listed in this table. synchronous shutter in a synchronous (snapshot or global) shutter, light integrati on occurs on all pixels in parallel, although subsequent readout is sequential. figure 7 shows the integration and readout sequence for the synchr onous shutter. all pixels ar e light sensitive at the same period of time. the whole pixel core is reset simultaneously, and after the integration time, all pixel values are sampled toge ther on the storage node inside each pixel. the pixel core is read out line by line after integration. note that the integration and re adout cycle can occur in parallel or in sequential mode (p ipelined or triggered). refer to the section image sensor timing and readout on page 18. figure 7. synchronous shutter operation table 11. overview of digital signals signal name i/o comments monitor_1 output output pin for integr ation timing, high during integration monitor_2 output output pin for dual slope in tegration timing, high during integration monitor_3 output output pin for triple slope integration timing, high during integration int_time_3 input integration pin triple slope int_time_2 input integration pin dual slope int_time_1 input integration pin first slope reset_n input sequencer reset, active low clk input system clock (630 mhz) spi_cs input spi chip select spi_clk input clock of the spi spi_in input data line of the spi, serial input spi_out output data line of the spi, serial output time axis line number integration time burst readout ti common reset common sample&hold flash could occur here [+] feedback
cyil2sm1300aa document number: 001-24599 rev. *c page 10 of 41 non destructive readout (ndr) figure 8. principle of non destructive readout the sensor can also be read out in a nondestructive method. after a pixel is initially reset, it can be read multiple times, wi thout being reset. you can record the initial reset level and all intermediat e signals. high light levels saturate the pixels quickly, but a useful signal is obtained from the early samples. for low light levels, the later or latest samples must be used. essentially, an active pixe l array is read multiple times, and reset only once. the external system intelligence interprets the data. table 12 on page 10 summarizes the advantages and disadvantages of nondestructive readout. note that the amount of samples taken with one initial reset is programmable in the nr_of_ndr_steps register. if nr_of_ndr_step s is one, the sensor operates in the default met hod, that is one reset and one sample. th is is called the disable nondestructive rea d out mode. when nr_of_ndr_steps is two, there is one reset and two samples , and so on. in the slave mode, nothing changes on the protocol of the signals int_time_*. the sequencer suppresses the internal reset signal to the pixel array. sequencer the sequencer generates the complete internal timing of the pixel array and the readout. the timing can be controlled by the us er through the spi register settings. the sequencer operates on the sa me clock as the data block. this is a division by 10 of the input clock (internally divided). ta b l e 1 3 lists the internal registers. these registers are discussed in detail in the section detailed description of internal registers on page 15. table 12. advantages and disadvantages of non destructive readout advantages disadvantages low noise, because it is true cds system memo ry required to record the reset level and the intermediate samples high sensitivity. the conversion capacitance is kept low. re quires multiples readings of each pixel, so there is higher data throughput high dynamic range. the results include signals for short and long integration times. requires system level digital calculations table 13. internal registers block register name address [6..0] field reset value description mbs (reserved) fix1 0 [7:0] 0x00 reserved, fixed value fix2 1 [7:0] 0xff reserved, fixed value fix3 2 [7:0] 0x00 reserved, fixed value fix4 3 [7:0] 0x00 reserved, fixed value fix5 4 [7:0] ?0x08? reserved, fixed value time [+] feedback
cyil2sm1300aa document number: 001-24599 rev. *c page 11 of 41 lvds clk divider lvdsmain 5 [3:0] ?0110? lvds trim [7:4] 0 clkadc phase lvdspwd1 6 [7:0] 0x00 power down channel 7:0 lvdspwd2 7 [5:0] 0 power down channel 13:8 [6] 0 power down all channels [7] 0 lvds test mode fix6 8 [7:0] 0x00 reserved, fixed value afe afebias 9 [3:0] ?1000? afe current biasing afemode 10 [2:0] ?111? vrefp, vrefm settings [5:3] ?000? pga settings [6] 0 power down afe afepwd1 11 [7:0] 0x00 power down adc_channel_2x 7 to 0 afepwd2 12 [3:0] 0x00 power down adc_channel_2x 11 to 8 bias block bandgap 13 [0] ?0? power down bandgap and currents [1] ?1? external resistor [2] ?0? external voltage reference [5:3] ?000? bandgap trimming image core imcmodes 14 [0] 0 power down [1] ?1? enable vrefcol regulator [2] ?1? enable precharge regulator [3] 0 disable internal bias for vprech [4] ?1? disable column load [5] ?0? clkmain invert fix7 15 [7:0] 0x00 reserved, fixed value fix8 16 [7:0] 0x00 reserved, fixed value imcbias1 17 [3:0] ?1000? bias colfpn dac buffer [7:4] ?1000? bias precharge regulator imcbias2 18 [3:0] ?1000? bias pixel precharge level [7:4] ?1000? bias column ota imcbias3 19 [3:0] ?1000? bias column unip fast [7:4] ?1000? bias column unip slow imcbias4 20 [3:0] ?1000? bias column load [7:4] ?1000? bias column precharge table 13. internal registers (continued) block register name address [6..0] field reset value description [+] feedback
cyil2sm1300aa document number: 001-24599 rev. *c page 12 of 41 data block fix9 21 [7:0] 0x20 reserved, fixed value fix10 22 [7:0] 0xc0 reserved, fixed value dataconfig1 23 [1:0] 0x00 reserved, fixed value [2] 0 ?1?: enables user upload of dacvrefadc register value ?0?: keeps default value [3] 0 enable prbs generation [4] 0 reserved, fixed value [5] 0 reserved, fixed value [7:6] 0x03 training pattern inse rted to sync lvds receivers dataconfig2 24 [7:0] 0x2a training pattern inserted to sync lvds receivers fix11 25 [7:0] 0 reserved, fixed value dacvrefadc 26 [7:0] 0x80 input to dac to se t the offset at the input of the adc fix12 27 [7:0] 0x80 reserved, fixed value fix13 28 [7:0] reserved, fixed value fix14 29 [7:0] reserved, fixed value datachannel0_1 30 [0] 0 bypass the data block [1] 0 enables the fpn correction [2] 0 overwrite incoming adc data by the data in the testpat register [3] 0 reserved, fixed value [5:4] 0x00 pattern inserted to generate a test image datachannel0_2 31 [7:0] 0x00 pattern inserted to generate a test image datachannel1_1 32 [0] 0 bypass the data block [1] 0 enables the fpn correction [2] 0 overwrite incoming adc data by the data in the testpat register [3] 0 reserved, fixed value data block (continued) [5:4] 0x00 pattern inserted to generate a test image datachannel1_2 33 [7:0] 0x00 pattern inserted to generate a test image datachannel12_1 54 [0] 0 bypass the data block [1] 0 enables the fpn correction [2] 0 overwrite incoming adc data by the data in the testpat register [3] 0 reserved, fixed value [5:4] 0x00 pattern inserted to generate a test image datachannel12_2 55 [7:0] 0x00 pattern ins erted to generate a test image table 13. internal registers (continued) block register name address [6..0] field reset value description [+] feedback
cyil2sm1300aa document number: 001-24599 rev. *c page 13 of 41 sequencer seqmode1 56 [0] 0 enables image capture [1] 1 ?1?: master mode, inte gration timing is generated on-chip ?0?: slave mode, integrat ion timing is controlled off-chip through int_time1, int_time2 and int_time3 pins [2] 0 ?0?: pipelined mode ?1?: triggered mode [3] 0 enables(?1?)/disables(?0?) subsampling [4] 0 ?1?: color subsampling scheme: 1:1: 0:0:1:1:0:0 ?0?: b&w subsampling scheme: 1:0:1:0:1 [5] 0 enable dual slope [6] 0 enable triple slope [7] 0 enables continued row select (that is, assert row select during pixel read out) seqmode2 57 [4:0] ?10000? must be overwritte n with?10001? to this register after startup, before readout. [6:5] ?00? number of active windows: ?00?: 1 window ?01?: 2 windows ?10?: 3 windows ?11?: 4 windows seqmode3 58 [0] ?1? enables the generation of the crc10 on the data and sync channels [1] ?0? not applicable [2] ?0? enable column fpn calibration [5:3] ?001? number of frames in nondestructive read out: ?000?: invalid ?001?: one reset, one sample (default mode) ?010?: one reset, two samples ? [6] 0 controls the granularity of the timer settings (only for those that have ?granularity selectable? in the description): ?0?: expressed in number of lines ?1?: expressed in clock cycles (multiplied by 2**seqmode4[3:0]) [7] 0 allows delaying the syncing of events that happen outside of rot to the next rot. this avoids image artefacts. table 13. internal registers (continued) block register name address [6..0] field reset value description [+] feedback
cyil2sm1300aa document number: 001-24599 rev. *c page 14 of 41 seqmode4 59 [3:0] 0x00 multiplier factor (=2**seqmode4[3:0]) for the timers when working in clock cycle mode [5:4] 0x0 selects the s ource signals to put on the digital test pins (monitor pins): ?00?: integration time settings ?01?: eos signals ?10?: frame sync signals ?11?: functional test mode [6] ?0? reverse read out in x direction [7] ?0? reverse read out in y direction window1_1 60 [7:0] 0x00 y start address for window 1 window1_2 61 [1:0] 0x00 y start address for window 1 [7:2] 0x00 x start add ress for window 1 window1_3 62 [7:0] 0xff y end address for window 1 window1_4 63 [1:0] 0x3 y end address for window 1 [7:2] 0x36 x width for window 1 window2_1 64 [7:0] 0x00 y start address for window 2 window2_2 65 [1:0] 0x00 y start address for window 2 [7:2] 0x00 x start add ress for window 2 window2_3 66 [7:0] 0xff y end address for window 2 window2_4 67 [1:0] 0x3 y end address for window 2 [7:2] 0x36 x width for window 2 window3_1 68 [7:0] 0x00 y start address for window 3 window3_2 69 [1:0] 0x00 y start address for window 3 [7:2] 0x00 x start add ress for window 3 window3_3 70 [7:0] 0xff y end address for window 3 window3_4 71 [1:0] 0x3 y end address for window 3 [7:2] 0x36 x width for window 3 window4_1 72 [7:0] 0x00 y start address for window 4 window4_2 73 [1:0] 0x00 y start address for window 4 [7:2] 0x00 x start add ress for window 4 window4_3 74 [7:0] 0xff y end address for window 4 window4_4 75 [1:0] 0x3 y end address for window 4 [7:2] 0x36 x width for window 4 res_length1 76 [7:0] 0x02 length of pix_rst (granularity selectable) res_length2 77 [7:0] 0x00 length of pix_rst (granularity selectable) res_dsts_length 78 [7:0] 0x01 length of resetds and resetts (granularity selectable) tint_timer1 79 [7:0] 0xff l ength of integration time (granularity selectable) tint_timer2 80 [7:0] 0x03 l ength of integration time (granularity selectable) tint_ds_timer1 81 [7:0] 0x40 length of ds integration time (granularity selectable) tint_ds_timer2 82 [1:0] 0x00 length of ds integration time (granularity selectable) tint_ts_timer1 83 [7:0] 0x0c length of ts integration time (granularity selectable) tint_ts_timer2 84 [1:0] 0x00 length of ts integration time (granularity selectable) table 13. internal registers (continued) block register name address [6..0] field reset value description [+] feedback
cyil2sm1300aa document number: 001-24599 rev. *c page 15 of 41 detailed description of internal registers the registers must be changed only during idle mode, that is, when seqmode1[0] is ?0?. uploaded registers have an immediate effect on how the frame is read out. parameters uploaded during readout may have an undesired effect on the data coming out of the images. mbs block the register block contains registers for sensor testing and debugging. all registers in this block must remain unchanged after startup. lvds clock divider block this block controls division of the input clock for the lvds transmitters or receivers. this block also enables shutting down one or all lvds channels. for normal operation, this register block must remain un touched after startup. afe block this register block contains registers to shut down adc channels or the complete afe block. this block also contains the register for setting the pga gain: afe_mode[5:3]. refer to electrical specifications on page 5 for more details on the pga settings. biasing block this block contains several registers for setting biasing currents for the sensor. default values after startup must remain unchanged for normal operation of the sensor. image core block the registers in this block have an impact on the pixel array itself. default settings after startup must remain unchanged for normal operation of the image sensor. data block the data block is positioned in between the analog front end (output stage + adcs) and the lvds interface. it muxes the outputs of 2 adcs to one lvds block and performs some minor data handling: crc calculation and insertion training and test pattern generation the most important registers in this block are: dataconfig. the dataconfig1[7:6] and dataconfig2[7:0] registers insert a training pattern in the lvds channels to sync the lvds receivers. tint_black_timer 85 [7:0] 0x06 reserved, fixed value rot_timer 86 [7:0] 0x0d length of rot (granularity clock cycles) fot_timer 87 [7:0] 0x36 length of fo t (granularity clock cycles) fot_timer 88 [1:0] 0x01 length of fo t (granularity clock cycles) prechpix_timer 89 [7:0] 0x7c l ength of pixel precharge (granularity clock cycles) prechpix_timer 90 [1:0] 0x00 l ength of pixel precharge (granularity clock cycles) prechcol_timer 91 [7:0] 0x03 length of c olumn precharge (granularity clock cycles) rowselect_timer 92 [7:0] 0x09 length of rowselect (granularity clock cycles) sample_timer 93 [7:0] 0xf8 length of pixel _sample (granularity clock cycles) sample_timer 94 [1:0] 0x00 length of pixel _sample (granularity clock cycles) vmem_timer 95 [7:0] 0x10 l ength of pixel_vmem (granularity clock cycles) vmem_timer 96 [1:0] 0x01 l ength of pixel_vmem (granularity clock cycles) delayed_rdt_timer 97 [7:0] 0 readout delay for testing purposes (granularity selectable) delayed_rdt_timer 98 [7:0] 0 readout delay for testing purposes (granularity selectable fix29 99 [0] 0 reserved, fixed value fix30 100 [0] 0 reserved, fixed value fix31 101 [0] 0 reserved, fixed value fix32 102 [0] 0 reserved, fixed value fix33 103 [0] 0 reserved, fixed value fix34 104 [0] 0 reserved, fixed value, write 0x4 to it table 13. internal registers (continued) block register name address [6..0] field reset value description [+] feedback
cyil2sm1300aa document number: 001-24599 rev. *c page 16 of 41 datachannels. datachannelx_1 and datachannelx_2 (with x=0 to 12) are registers that allow you to enable or disable the fpn correction (datachannelx_1[1]), and generate a test pattern if necessary (datachannelx_1[5:4] and datachannelx_2[7:0]). sequencer block the sequencer block group registers allow enabling or disabling image sensor features that are driven by the onboard sequencer. this block consists of the following registers: seqmode1. the seqmode1 registers have the following subregisters: seqmode1[0]: enables image capt ure, must be '1' during image acquisition. seqmode1[1]: this subregister has two modes: '1': in this default mode the integration timing is generated on-chip. '0': in this slave mode, the in tegration timing must be generated through the int_time1, int_time2, and int_time3 pins. seqmode1[2]: this bit enables pipelined (0) or triggered (1) mode. seqmode1[3]: enable (1) or disable (0) subsampling. seqmode1[4]: this bit sets th e type of subsampling scheme used when subsampling is enabled. '1': color (1:1:0:0:1:1:0:0:1?) '0': black and white (1:0:1:0:1) seqmode1[5]: this bit enables or disables the dual slope integration. seqmode1[6]: this bit enables or disables the triple slope integration. seqmode2. the seqmode2 register consists of only two subregisters: seqmode2[4:0]: default value after startup is '10000', but this must be overwritten with the new value '10001' immediately after startup. seqmode3[6:5]: these two bits set the number of active windows: '00': 1 window '01': 2 windows '10': 3 windows '11': 4 windows (max) seqmode3. the seqmode3 register consists of the following subregisters: seqmode3[0]: this bit enables or disables the crc10 generation on the data and sync channels seqmode3[1]: enables or disables black level calibration seqmode3[2]: enables or disables column fpn correction seqmode3[5:3]: enables or disables, and sets the number of frames grabbed in nonde structive readout mode. '000': invalid '001': default, 1 reset, 1 sample '010': 1reset, 2 samples '011': 1 reset, 3 samples seqmode3[6]: controls the granularity of the timer settings (only for those that have 'granularity se lectable' in the description). as a result, all timer settings are se t either in number of applied clock cycles, or in the number of 'readout lines'. '0': expressed in number of lines '1': expressed in clock cycles (multiplied by 2**seqmode4 [3:0]) seqmode3[7]: allows syncing of events that happen outside of rot to be delayed to the next rot to avoid image artifacts. seqmode4. this register consists of four subregisters: seqmode4[3:0]: multiplier fact or (2**seqmode4[3:0]) for the timers when working in clock cycle mode. seqmode4[5:4]: selects the source signals to be put on the digital test pins (monitor1, monitor2, and monitor3 pins) "00": integration time settings "01": eos signals "10": frame sync signals "11": functional test mode seqmode4[6]: enables (1) and disables (0) reverse x read out. seqmode4[7]: enables (1) and disables (0) reverse y read out. y1_start (60 and 61, 10 bit). these registers set the y start address for window 1 (default window). x1_start (61, 6bit). this register sets the x start address for window 1 (default window). y1_end (62 and 63, 10 bit). these registers set the y end address for window 1 (default window). x1_kernels (63, 6 bit). this register sets the number of kernels or x width to be read out for window 1 (default window). y2_start (64 and 65, 10 bit). these registers set the y start address for window 2 (if enabled). x2_start (65, 6bit). this register sets the x start address for window 2 (if enabled). y2_end (66 and 67, 10 bit). these registers set the y end address for window 2 (if enabled). x2_kernels (67, 6 bit). this register sets the number of kernels or x width to be read out for window 2 (if enabled). y3_start (68 and 69, 10 bit). these registers set the y start address for window 3 (if enabled). x3_start (69, 6bit). this register sets the x start address for window 3 (if enabled). y3_end (70 and 71, 10 bit). these registers set the y end address for window 3 (if enabled). x3_kernels (71, 6 bit). this register sets the number of kernels or x width to be read out for window 3 (if enabled). y4_start (72 and 73, 10 bit). these registers set the y start address for window 4 (if enabled). x4_start (73, 6bit). this register sets the x start address for window 4 (if enabled). y4_end (74 and 75, 10 bit). these registers set the y end address for window 4 (if enabled). x4_kernels (75, 6 bit). this register sets the number of kernels or x width to be read out for window 4 (if enabled). [+] feedback
cyil2sm1300aa document number: 001-24599 rev. *c page 17 of 41 res_length (76 and 77). this register sets the length of the internal pixel array reset (how long are all pixel reset simultaneously). this value is expressed in 'number of lines' or in clock cycles (depends on seqmode3[6]). res_dsts_length. this register sets the length of the internal dual and triple slope reset pulses when enabled. this value is expressed in 'number of lines' or in clock cycles (depends on seqmode3[6]). tint_timer (79 and 80). this register sets the length of the integration time. this value is ex pressed in 'number of lines' or in clock cycles (depends on seqmode3[6]). tint_ds_timer (81 and 82). this register sets the length of the dual slope integration time. this value is expressed in 'number of lines' or in clock cycles (depends on seqmode3[6]). tint_ts_timer (83 and 84). this register sets the length of the triple slope integration time. this value is expressed in 'number of lines' or in clock cycles (depends on seqmode3[6]). data interface (spi) the serial 4-wire interface (or serial to parallel interface) uses a serial input or output to shift the data in or out the register buffer. the chip's configuration registers are accessed from the outside world through the spi protocol. a 4-wire bus runs over the chip and connects the spi i/os with the internal register blocks. the interface consists of: cs_n: chip select, when low the chip is selected clk: the spi clock in: master out, slave in, th e serial input of the register out: master in, slave out, the serial output of the register spi protocol the information on the data 'in' line is: a command bit c, indicating a wr ite ('1') or a read ('0') access 7-bit address 8-bit data word (in case of a write access) the data 'out' line is generally in high z mode, except when a read request is performed. data is always written on the bus on the falling edge of the clock, and sampled on the rising edge, as seen in figure 9 and figure 10 . this is valid for both the 'in' and 'out' bus. the system clock must be active to keep the spi uploads stored on the chip. the spi clock speed must be slower by a factor of 30 when compared to the system clock (315 mhz nominal speed). figure 9. write access (c='1') the 'out' line is held to high z. the data for the address a is transferred from the shift registe r to the active register bank (that is, sampled) on a rising edge of cs_n. only the register block with address a can write its data on the 'out' bus. the data on 'in' is ignored. figure 10. read access (c='0') [+] feedback
cyil2sm1300aa document number: 001-24599 rev. *c page 18 of 41 image sensor timing and readout the timing of the sensor consists of two parts. the first part is related to the exposure time and the control of the pixel. the second part is related to the read out of the image sensor. integration and readout are in para llel or triggered. in the first case, the integration time of frame i is ongoing during the readout of frame i-1. figure 11 shows this parallel timing structure. the readout of every frame starts with a fot, during which the analog value on the pixel diode is transferred to the pixel memory element. after this fot, the sensor is read out line by line. the read out of every line starts with a rot, during which the pixel value is put on the column lines. then the pixels are selected in groups of 24 (12 on rising edge, and 12 on the falling edge of the internal clock). so in total, 54 kernels of 24 pixels are read out every line. the internal timing is generated by the sequencer. the sequencer can operate in two modes: master mode and slave mode. in master mode, all internal timing is controlled by the sequencer, based on the spi settings. in slave mode, the integration timing is directly contro lled by over three pins, and the readout timing is still controlled by the sequencer. the seqmode1[1] register of the sp i selects between the master and slave modes. figure 11. global readout timing (parallel) pipelined shutter integration and readout occur in parallel and are continuous. you only need to start and stop th e batch of image captures. integration of frame n is always ongoing duri ng readout of frame n-1. th e readout of every frame starts with a fot, during whic h the analog value on the pixel diode is transferred to the pixel memory element. after this fot, the sensor is read out line by line . the readout of every line starts with a rot, during which the pixel va lue is put on the column lines. then the pixels are muxed in the correct adcs, processed, and then sent to the lvds output block. figure 12. integration and readout for pipelined shutter you have two options in the pipelined shutter mode. the first opt ion is to program the reset and integration through the config uration interface and let the sequencer handle integration time automatically . this mode is called master mode. the second option is to drive the integration time through an external pin. this mode is called slave mode. readout lines integration frame i+1 integration frame i+2 readout frame i readout frame i+1 fot l1 l2 l1024 ... rot k1 k2 k54 ... readout pixels reset n exposure time n reset n+1 exposure time readout n-1 readout n fot fot rot line readout int. time handling readout handling [+] feedback
cyil2sm1300aa document number: 001-24599 rev. *c page 19 of 41 programming the exposure time in master mode, the exposure time is configured in two distinct methods (controll ed by register seqmode3[6]): #lines: obvious, changing signals that cont rol integration time. they are always c hanged during rot to avoid any image artefact s. #clock cycles: must be multiplied by (2**seqmod e4[3:0]). when th e counter expires, changes are pu t into effect immediately. ass erting the configuration signal (seqmode3[7]) forces delaying signal updates until the next rot. ta b l e 1 4 lists the user programmable timer settings an d how they are interpreted by the hardware. note that the seqmode3[7] can also be used to sync the user signals in slave mode. the behavior is exactly the same. master mode in master mode the reset and exposure time is written in registers. figure 13. integration and image readout in master mode ensure that the added value of the regist ers res_length and tint_timer always exceeds the number of lines that are read out. th is is because the sequencer samples a new image after integration is co mplete, without checking if image readout is finished. enlargi ng res_length to accommoda te for this has no impact on image capture. table 14. user programmable timer settings setting granularity reg_res_length lines/cycles reg_tint_timer lines/cycles reg_tint_ds_timer lines/cycles reg_tint_ts_timer lines/cycles reg_rot_timer clock cycles reg_fot_timer clock cycles reg_sel_pre_timer clock cycles reg_precharge_timer clock cycles reg_sample_timer clock cycles reg_vmem_timer clock cycles reg_delayed_rdt_timer lines/cycles [+] feedback
cyil2sm1300aa document number: 001-24599 rev. *c page 20 of 41 slave mode in slave mode, the register values of res_ length and tint_timer are i gnored. the integration time is controlled by the int_time pin. the relationship between the input pin an d the integration time is shown in figure 14 . when the input pin int_time is asserted, the pixel array goes out of reset and exposure can begin. when int_time goes low again and the desired exposur e time is reached, the imag e is sampled and read out can begin. figure 14. integration and image readout in slave mode changing a pixel's reset level during line readout might result in image artefacts during a small transient period. as a result , it is advised to only change the value of int_time during rot. triggered shutter the two main differences in the pipelined shutter mode are: one single image is read upon every user action. integration (and read out) is under control of the user through pin int_time. this means that for every frame, you need to manually intervene. the pixel array is kept in reset state until you assert the in t_time input. similar to the pipelined shutter mode, there is a master mode in which the s equencer can control the integration time, o r a slave mode in which you can define the integration time. figure 15. integration and readout for triggered shutter the possible applications for this triggered shutter mode are: synchronize external flash with exposure apply extremely long integrat ion times (only in slave mode) reset exposure time n reset exposure time n int. time handling readout handling readout n fot rot line readout int_time1 read out n+1 n+1 fot reset [+] feedback
cyil2sm1300aa document number: 001-24599 rev. *c page 21 of 41 master mode in this mode, a rising edge on int_time1 pin is used to trigger the start of integration and read out . the tint_timer defines the integration time independent of the assertion of the input pin int_time1. after the integration time counter runs out, the fot automatically starts and the image readout is done. during readout, the image array is kept in reset. a request for a new frame is started again when a new rising edge on int_time is detected. the time of the falling edge is not important in this mode. slave mode integration time control is identical to the pipelined shutter slave mode. the int_time1 pin controls the start of integration. when int_time is deasserted, the fot starts (analog value on the pixel diode is transferred to the pixel memory element). only at that time, image read out can start (similar to the pipelined read out). during read out, the image array is kept in reset. a request for a new frame is started when int_time goes high again. windowing a fully configurable window can be selected for readout. figure 16. window selected for readout the parameters to configure this window are: x_start. the sensor reads out 24 pixels in one single clock cycle. the granularity of configuring the x start position is also 24. every value written to the window x_2 register must be multiplied by 24 to find the corresponding column in the pixel array. x_kernels. the number of columns that is read out (x_kernels*24 in full frame mode) in subsampling mode x_kernels*48 represents the nu mber of columns over which subsampling is done. the x_kernels value must be written to the windowx_4 register. y_start. the starting line of the readout window, granularity of 1. note that in subsample mode, the correct y_start position must be uploaded (exact value depends on color or b/w subsampling mode). this value must be written to the windowx_1 and windowx_2 register. y_end. the end line of the readout window, granularity of 1. in all cases (even in reverse scan), y_end are larger than y_start. note that in subsample mode, the correct y_end position must be uploaded (exact value depends on color or b/w subsampling mode). this value must be written to the windowx_3 and windowx_4 register. in case of windowing, the effect ive readout time is smaller than in full frame mode, because only the relevant part of the image array is accessed. as a result, it is possible to achieve higher frame rates. 1024 p ixels 1280 p ixels xstar t xkernel y_ en d y star t [+] feedback
cyil2sm1300aa document number: 001-24599 rev. *c page 22 of 41 reverse scan reverse scanning is supported in the x and y direction. line 0 (first line on the output) is the top line in normal mode and th e bottom line in reverse scanning, as shown in figure 17 . as a result, the line numbers always in crement. when reverse scanning in x, the operation is analogous. to enable reverse readout in x and y, se t the seqmode4[6:7] bits. in a ddition, the y_start and x_start addresses must be changed to the new starting address. figure 17. normal and reverse scanning in y multiple windows the sequencer supports the readout of four different windows, randomly positioned over the pixel array. the images are read out sequentially. that is, window 1 is read out before window 2, even if both windows show some overlap. next, windows 3 and 4 are read out. you can configure the number of wi ndows used in the application (one to four). figure 18 shows how to configure two windows spread over the image array. figure 18. multiple windows read from the same pixel array [+] feedback
cyil2sm1300aa document number: 001-24599 rev. *c page 23 of 41 figure 19 shows the sequence of integration and read out for multiple windows. the handling of integration time is identical to the single window mode (except that in this case , the maximum integration time is equal to the sum of the y_widths of the two windo ws). read out starts with a fot that is similar to single window mode. after the fot, all lines of window 1 are read, followed by th e lines of window 2. figure 19. exposure and read out of multiple windows if the x size of the windows are not identical, the integration time in function of the number of lines read presents multiple slopes (proportional to the x size of these windows). because this can cause confusion when programmi ng the integration time, it is easier to configure all timer registers using the clock cycle configuration instead of th e 'line' configuration. multiple slopes dynamic range can be extended by the multiple slope capabilities of the sensor. the four colored lines in figure 20 represent analog signals of the photodiode of four pixels, which decrease as a result of exposure. the slope is determined by the amount of light at each pixe l (the more light, the steeper the slope). when the pixels reach the saturation level, the analog does not change despite further exposure. without the multiple slope capabilities, the pixels p3 and p4 are saturated before the end of the exposure time, and no signal is received. however, when using multiple slopes, the analog signal is reset to a second or third reset level (lower than the original) before the integration time ends. the anal og signal starts decreasing with the same slope as before, and pi xels that were saturated before could be nonsaturated at read out time. for pixels that never reach any of the reset levels (f or example, p1 and p2) there is no difference between single and multiple slope operation. by choosing the time stamps of the double and triple slope resets (typical at 90% and 99% of the in tegration, configurable by the user), it is possible to have a nonsaturated pixel value even for pixels that receive a huge amount of light. figure 20. dynamic range extended by multiple slope capability reset n exposure time n reset n+1 exposure time int. time handling readout handling readout n fot fot rot line readout window 1 line readout window 2 readout n window 2 readout n-1 window 1 readout n-1 window 2 t [+] feedback
cyil2sm1300aa document number: 001-24599 rev. *c page 24 of 41 the reset levels are configured through external (power) pins. in master mode, the time stamps of the double and triple slope r esets are configured in a method similar to configuring the exposure time. the time stamps are enabled through the registers seqmode1[5] and seqmode1[6], and their values are express ed in line or clock cycles in the regist ers reg_tint_ds_timer and reg_tint_ts_time r. figure 21. triple slope timing in master mode in slave mode, the values of res_length, tint_timer, tint_ds_ti mer, and tint_ts_timer in the configuration registers are ignore d. you have full control through the pins int_time, int_time_ds, and int _time_ts. you must configure the multiple slope parameters for the application and interpret the pixel data accordingly. figure 22. triple slope timing in slave mode [+] feedback
cyil2sm1300aa document number: 001-24599 rev. *c page 25 of 41 column fpn correction the column fpn of the sensor is improved by the offset correction of the columns. at the start of every frame, before read out of the actual lines is done, a fixed voltage is applied at the columns and these values are read out like a real data line. inside the data block, the 'pixel' data for that line is stored in an on-chip fpn memory. when the correction is enabled, the corresponding fpn value is subtracted from the incoming pixel data. this fpn correction must be enabled for every output separately. the registers used to configure the correction are: datachannelx_1 with x from 0 to 11 . the field [1] of these registers enables the offset corre ctions of the specific output channel. note do not change the settings of datachannel12_1. this channel contains synchronization data, not pixel data. if fpn correction is enabled on this channel, the synchronization data becomes corrupt. seqmode3 . the field[2] must be '1'. it enables the generation of the line of reference voltages at the columns. figure 23 and figure 24 show the effect of enabling the column fpn correction. these images are magnified up to five times. figure 23. dark image without fpn correction (5x amplified) figure 24. dark image with fpn correction enabled (5x amplified) [+] feedback
cyil2sm1300aa document number: 001-24599 rev. *c page 26 of 41 image format and read out protocol the active area read out by the sequencer in full frame mode is shown in figure 25 . before the actual pixels are read out, one dummy line is read to enable column fpn calibration. a reference volta ge is applied to the columns and the entire line is read as if real pixel values are placed on the columns. pixels are always read in multiples of 24 (one value to every ch annel in the afe). the last time slot contains not only valid p ixels, but also two dummy columns, six grey columns, and eight black columns. figure 25. sensor read out format [+] feedback
cyil2sm1300aa document number: 001-24599 rev. *c page 27 of 41 the following sections discuss the appearance of the output (dat a and synchronization codes) in several relevant configurations . twelve output channels are connected to the 24 adcs and handl e the data. one additional channel co ntains all the synchronizatio n codes for the receiver. this indicates, fo r example, the start of a frame, the end of a frame, whether the data channels contai n data, crc, a training pattern, and so on. the sequencer provides the sy nchronization channel with the co rrect synchronization or prot ocol signals, as shown in figure 26 . the synchronization codes are listed in ta b l e 1 5 . note that a fs also serves as ls, and vice versa. figure 26. data and sync channel overview table 15. synchronization codes sync code abbreviation 10-bit code frame start fs 0x059 line start ls 0x056 frame end fe 0x05a line end le 0x055 grey/black cols gbc 0x0a9 crc crc 0x0a6 fpn stored values fpn 0x13c normal data d 0x193 training pattern t t [+] feedback
cyil2sm1300aa document number: 001-24599 rev. *c page 28 of 41 full frame mode in this operation mode, the entire sensor shown in figure 25 on page 26 is read out. figure 27 shows the internal state of the sequencer, and the behavior of the data and sync channels (overview and detail of one line). figure 27. full frame mode read out data channel sync channel data channel sync channel sequencer internal state line 0 line 1 line 1022 line 1023 black timeslot timeslot timeslot timeslot 53 timeslot 54 crc timeslot t t fs d d d d d d d l e gb c cr c t t fot rot rot rot rot 1 3 2 [+] feedback
cyil2sm1300aa document number: 001-24599 rev. *c page 29 of 41 this table provides a detailed overview of remapping one full row read out. table 16. remapping scheme for one row timeslot ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch8 ch9 ch10 ch11 1a 0246810121416182022 1b 1357911131517192123 2a 47 45 43 41 39 37 35 33 31 29 27 25 2b 46 44 42 40 38 36 34 32 30 28 26 24 3a 48 50 52 54 56 58 60 62 64 66 68 70 3b 49 51 53 55 57 59 61 63 65 67 69 71 4a 95 93 91 89 87 85 83 81 79 77 75 73 4b 94 92 90 88 86 84 82 80 78 76 74 72 5a 96 98 100 102 104 106 108 110 112 114 116 118 5b 97 99 101 103 105 107 109 111 113 115 117 119 6a 143 141 139 137 135 133 131 129 127 125 123 121 6b 142 140 138 136 134 132 130 128 126 124 122 120 7a 144 146 148 150 152 154 156 158 160 162 164 166 7b 145 147 149 151 153 155 157 159 161 163 165 167 8a 191 189 187 185 183 181 179 177 175 173 171 169 8b 190 188 186 184 182 180 178 176 174 172 170 168 9a 192 194 196 198 200 202 204 206 208 210 212 214 9b 193 195 197 199 201 203 205 207 209 211 213 215 10a 239 237 235 233 231 229 227 225 223 221 219 217 10b 238 236 234 232 230 228 226 224 222 220 218 216 11a 240 242 244 246 248 250 252 254 256 258 260 262 11b 241 243 245 247 249 251 253 255 257 259 261 263 12a 287 285 283 281 279 277 275 273 271 269 267 265 12b 286 284 282 280 278 276 274 272 270 268 266 264 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 53a 1248 1250 1252 1254 1256 1258 1260 1262 1264 1266 1268 1270 53b 1249 1251 1253 1255 1257 1259 1261 1263 1265 1267 1269 1271 54a 1295 1293 1291 1289 1287 1285 1283 1281 1279 1277 1275 1273 54b 1294 1292 1290 1288 1286 1284 1282 1280 1278 1276 1274 1272 crc [+] feedback
cyil2sm1300aa document number: 001-24599 rev. *c page 30 of 41 single window mode containing timeslot 54 in this operation mode, only pa rt of the sensor is read out, as shown by the shaded area in figure 28 . a clear distinction is made with the single window mode that does not contain the timeslot 54, be cause the output synchr onization protocol is slightly different . figure 28. single window containing timeslot 54 figure 29 shows the internal state of the sequencer, and the behavior of the data and sync channels (overview and detail of one line) for this window mode. figure 29. waveform for single window containing timeslot 54 data channel sync channel sequencer internal state line ys line ys+1 line ye black timeslot x timeslot x+1 53 54 crc t l s d f e gb c cr c fot rot rot rot data channel sync channel timeslot timeslot timeslot t t t d d dd rot [+] feedback
cyil2sm1300aa document number: 001-24599 rev. *c page 31 of 41 single window mode not containing timeslot 54 in this operation mode, only part of the sensor is read out, as shown in figure 30 . although the window is defined as not containing any data from timeslot 54, it is read out to provide information on grey and black columns to the user. this results in some mi nor differences between the waveforms from figure 29 on page 30 and figure 31 . figure 30. single window not containing timeslot 54 figure 31 shows the internal state of the sequencer, and the behavior of the data and sync channels (overview and detail of one line) for this window mode. figure 31. waveform for single window not containing timeslot 54 note that the dummy black line is read completely. reading out multiple windows does not differ fr om combining the windowed modes in sections single window mode containing timeslot 54 on page 30 and single window mode not containing timeslot 54 . the dummy black line again spans the entire width of the sensor and is processed only once, before all configured windows are read. the dummy black line is independent of the windo w sizes. data channel sync channel sequencer internal state line ys line ys +1 line ye black timeslot xstart timeslot timeslot xend timeslot 54 crc timeslot t t l s d d d d l e t gb c cr c t t fot rot rot rot rot timeslot xend-1 d d [+] feedback
cyil2sm1300aa document number: 001-24599 rev. *c page 32 of 41 pin list table 17. pin placement layout (top view) 1 2 3 4 5 6 7 8 9 10 11 12 131415161718192021222324 a 134 130 127 124 121 118 115 112 109 106 103 100 99 96 93 90 87 84 81 78 75 72 69 65 b * 131 128 125 122 119 116 113 110 107 104 101 98 95 92 89 86 83 80 77 74 71 68 * c 133 132 129 126 123 120 117 114 111 108 105 102 97 94 91 88 85 82 79 76 73 70 67 66 d e f g h j k top view l m n p q r s t 135 139 140 137 145 * 5 7 * 17 19 * * 31 29 * 43 41 * 54 62 60 59 64 u 136 144 141 138 146 * 8 6 * 20 18 * * 30 32 * 42 44 * 53 61 55 58 63 v 149 147 142 * 1 3 9 11 13 15 21 23 25 27 33 35 37 39 45 47 * 52 57 50 w150148143 * 2 4 10 12 14 16 22 24 2628343638404648 * 515649 [+] feedback
cyil2sm1300aa document number: 001-24599 rev. *c page 33 of 41 table 18. pin list nr pin name type direction description position 1 clkoutp lvds o p clk output channel v5 2 clkoutn lvds o n clk output channel w5 3 chp[0] lvds o p output channel [0] v6 4 chn[0] lvds o n output channel [0] w6 5 gndlvds supply i/o lvds ground t7 6 gndadc supply i/o adc ground u8 7 vddadc supply i/o adc power t8 8 vddlvds supply i/o lvds power u7 9 chp[1] lvds o p output channel [1] v7 10 chn[1] lvds o n output channel [1] w7 11 chp[2] lvds o p output channel [2] v8 12 chn[2] lvds o n output channel [2] w8 13 chp[3] lvds o p output channel [3] v9 14 chn[3] lvds o n output channel [3] w9 15 chp[4] lvds o p output channel [4] v10 16 chn[4] lvds o n output channel [4] w10 17 gndlvds supply i/o lvds ground t10 18 gndadc supply i/o adc ground u11 19 vddadc supply i/o adc power t11 20 vddlvds supply i/o lvds power u10 21 chp[5] lvds o p output channel [5] v11 22 chn[5] lvds o n output channel [5] w11 23 chp[6] lvds o p output channel [6] v12 24 chn[6] lvds o n output channel [6] w12 25 chp[7] lvds o p output channel [7] v13 26 chn[7] lvds o n output channel [7] w13 27 chp[8] lvds o p output channel [8] v14 28 chn[8] lvds o n output channel [8] w14 29 gndlvds supply i/o lvds ground t15 30 gndadc supply i/o adc ground u14 31 vddadc supply i/o adc power t14 32 vddlvds supply i/o lvds power u15 33 chp[9] lvds o p output channel [9] v15 34 chn[9] lvds o n output channel [9] w15 35 chp[10] lvds o p output channel [10] v16 36 chn[10] lvds o n output channel [10] w16 37 chp[11] lvds o p output channel [11] v17 38 chn[11] lvds o n output channel [11] w17 39 n/a not assigned v18 40 n/a not assigned w18 41 gndlvds supply i/o lvds ground t18 42 gndadc supply i/o adc ground u17 [+] feedback
cyil2sm1300aa document number: 001-24599 rev. *c page 34 of 41 43 vddadc supply i/o adc power t17 44 vddlvds supply i/o lvds power u18 45 clkinp lvds i lvds input clock 315 mhz p-node v19 46 clkinn lvds i lvds input clock 315 mhz n-node w19 47 syncp lvds o lvds sync and output v20 48 syncn lvds o lvds sync and output w20 49 gnddig supply i/o digital ground w24 50 vdddig supply i/o digital power supply v24 51 cap_vrefm analog o lower limit adc range decoupling w22 52 cap_vrefp analog o higher limit adc range decoupling v22 53 gndadc supply i/o adc ground u20 54 vddadc supply i/o adc power supply t20 55 gnddig supply i/o digital ground u22 56 gndbuf supply i/o column buffers ground w23 57 vddbuf supply i/o column buffers supply v23 58 gndana supply i/o column buffers ground u23 59 vddana supply i/o column buffers supply t23 60 vpix supply i/o pixel core supply t22 61 gndpix supply i/o pixel core ground u21 62 vsamp supply i/o image core select and sample supply t21 63 gndadc supply i/o adc ground u24 64 vdddig supply i/o digital power supply t24 65 nbias_colload analog o column bias decouple a24 66 test_ena cmos i scan pin for sequencer c24 67 int_time1 cmos i integration pin first slope c23 68 int_time2 cmos i integration pin dual slope b23 69 int_time3 cmos i integration pin triple slope a23 70 monitor1 cmos o output pin for integration timing, high during integration c22 71 monitor2 cmos o output pin for dual slope integration timing, high during integration b22 72 monitor3 cmos o output pin for triple slope integration timing, high during integration a22 73 cap_vrefadc analog o adc black reference decoupling c21 74 vpix supply i/o pixel core supply b21 75 cap_vrefcm analog o adc common mode decoupling a21 76 reset_n cmos i/o chip reset (active low) c20 77 scan_en cmos i dft scan enable b20 78 scan_clk cmos i dft clock a20 79 scan_clk_en cmos i dft clock enable c19 80 gndpix supply i/o pixel core ground b19 81 gnddig supply i/o digital ground a19 82 vdddig supply i/o digital power supply c18 83 vpix supply i/o pixel core supply b18 table 18. pin list (continued) nr pin name type direction description position [+] feedback
cyil2sm1300aa document number: 001-24599 rev. *c page 35 of 41 84 pixdiode analog o pixel diode current pin a18 85 gndpix supply i/o pixel core ground c17 86 vsamp supply i/o image core select and sample supply b17 87 vresetab supply i/o anti blooming lower reset level a17 88 vprech supply i/o pixel precharge level/decoupling pin c16 89 vmemh supply i/o pixel memory reference high b16 90 vmeml supply i/o pixel memory reference low a16 91 vreset supply i/o pixel reset level c15 92 vresetds supply i/o pixel dual slope reset level/decoupling pin b15 93 vresetts supply i/o pixel triple slope reset level/decoupling pin a15 94 vresetab supply i/o anti blooming lower reset level c14 95 gndpix supply i/o pixel core ground b14 96 vresetts supply i/o pixel triple slope reset level/decoupling pin a14 97 vresetds supply i/o pixel dual slope reset level/decoupling pin c13 98 vreset supply i/o pixel reset level b13 99 vsamp supply i/o image core select and sample supply a13 100 vmeml supply i/o pixel memory reference low a12 101 vmemh supply i/o pixel memory reference high b12 102 vprech supply i/o pixel precharge level/decoupling pin c12 103 n/a not assigned a11 104 gndpix supply i/o pixel core ground b11 105 vresetab supply i/o anti blooming lower reset level c11 106 vresetts supply i/o pixel triple slope reset level/decoupling pin a10 107 vresetds supply i/o pixel dual slope reset level/decoupling pin b10 108 vreset supply i/o pixel reset level c10 109 vmeml supply i/o pixel memory reference low a9 110 vmemh supply i/o pixel memory reference high b9 111 vprech supply i/o pixel precharge level/decoupling pin c9 112 vresetab supply i/o anti blooming lower reset level a8 113 vsamp supply i/o image core select and sample supply b8 114 gndpix supply i/o pixel core ground c8 115 ibiaspre analog i external current bias fo r vprech (not connected by default) a7 116 vpix supply i/o pixel core supply b7 117 vdddig supply i/o digital power supply c7 118 gnddig supply i/o digital ground a6 119 gndpix supply i/o pixel core ground b6 120 n/a not assigned c6 121 n/a not assigned a5 122 n/a not assigned b5 123 n/a not assigned c5 124 cap_vrefcm analog o adc common mode decoupling a4 125 vpix supply i/o pixel core supply b4 126 cap_vrefadc analog o adc black reference decoupling c4 table 18. pin list (continued) nr pin name type direction description position [+] feedback
cyil2sm1300aa document number: 001-24599 rev. *c page 36 of 41 127 spics cmos i spi chip select a3 128 spiclk cmos i spi clock b3 129 spiin cmos i spi serial input c3 130 spiout cmos o spi serial output a2 131 mbsbus[0] analog i/o first mixed boundary scan bus b2 132 mbsbus[1] analog i/o second mixed boundary scan bus c2 133 refbg analog i/o external bias resistor c1 134 cmdmbs analog i bias current for mbs buffers a1 135 vdddig supply i/o digital power supply t1 136 gndadc supply i/o adc ground u1 137 vsamp supply i/o image core select and sample supply t4 138 gndpix supply i/o pixel core ground u4 139 vpix supply i/o pixel core supply t2 140 vddana supply i/o analog power supply t3 141 gndana supply i/o analog ground u3 142 vddbuf supply i/o column buffers supply v3 143 gndbuf supply i/o column buffers ground w3 144 gnddig supply i/o digital ground u2 145 vddadc supply i/o adc power supply t5 146 gndadc supply i/o adc ground u5 147 cap_vrefp analog i/o higher limit adc range decoupling v2 148 cap_vrefm analog i/o lower limit adc range decoupling w2 149 vdddig supply i/o digital power supply v1 150 gnddig supply i/o digital ground w1 table 18. pin list (continued) nr pin name type direction description position [+] feedback
cyil2sm1300aa document number: 001-24599 rev. *c page 37 of 41 package information figure 32. package outline drawing with glass the total distance from the bottom of the pga package (same as the pcb plane) to the top of the die surface is 19.016 mm. 001-44705 ** [+] feedback
cyil2sm1300aa document number: 001-24599 rev. *c page 38 of 41 figure 33. pixel active area dimensions package with glass cross section figure 34. package cross section [+] feedback
cyil2sm1300aa document number: 001-24599 rev. *c page 39 of 41 die specifications figure 35. die specifications 1450 50 um 1700 50 um [+] feedback
cyil2sm1300aa document number: 001-24599 rev. *c page 40 of 41 glass lid the lupa 1300-2 monochrome and color image sensor uses a glass lid without any coatings. figure 36 shows the transmission characteristics of the glass lid. as seen in figure 36 , no infrared attenuating color filter glass is used. you must provide this filter in the optical path when color devices are used. figure 36. transmission cha racteristics of the glass lid handling precautions for proper handling and storage conditions, refer to the cypress application note an52561 at www.cypress.com . limited warranty cypress image sensor business unit warrants that the image sensor products mentioned here, if properly used and serviced, conform to the seller's published specifications. they are free from defects in material and workmanship for one (1) year following the date of shipment. application note references an54468 : interfacing the lupa1300-2 with fpga. this application note describes the interface between the lupa 1300-2 and the fpga, as implemented in the lupa 1300-2 demonstration kit cyil2sm1300-eval. it also provides an overview of the architecture of the demonstration kit and the method used to synchronize channels. an54214: high speed layout guidelines for the lupa 1300-2 image sensor [+] feedback
document number: 001-24599 rev. *c revised september 18, 2009 page 41 of 41 all products and company names mentioned in this document may be the trademarks of their respective holders. cyil2sm1300aa ? cypress semiconductor corporation, 2007-2009. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreemen t with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significa nt injury to the user. the inclusion of cypress products in life-support systems application implies that the manufact urer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and international treaty provisions . cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page sales, solutions, and legal information worldwide sales and design support cypress offers standard and customized cmos image sensors for co nsumer as well as industrial and professional applications. consumer applications include solutions for fast growing high speed machine vision, motion monitoring, medical imaging, intelli gent traffic systems, security, and barcode applications. cypress's cust omized cmos image sensors are characterized by very high pix el counts, large area, very high frame rates, la rge dynamic range, a nd high sensitivity. cypress maintains a worldwide network of offices, solution cent ers, manufacturer's representatives, and distributors. for more information on image sensors, please contact imagesensors@cypress.com . document title: cyil2sm1300aa lupa 1300-2: high speed cmos image sensor document number: 001-24599 revision ecn orig. of change submission date description of change ** 1438663 fpw 09/04/07 initial cypress release. *a 2649816 nvea/aesa 03/17/2009 updated parameters in table 4 on page 5. updated data sheet template. added handling precautions section. *b 2745961 nvea/aesa 07/29/2009 updated ?features? on page 1, ?description? on page 1, and ?overview? on page 2 updated table on page 1 updated table 13 on page 10 modified ?handling precautions? on page 40 added ?application note references? on page 40 *c 2765859 nvea/aesa 09/18/2009 updated ordering information table [+] feedback

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